http://seeker.dice.com/jobsearch/servlet/JobSearch?op=302&dockey=xml/2/7/27aceebcb1044d87926d0abeea5ab780@endecaindex&source=19&FREE_TEXT=network+engineer&rating=99
The Job Ad reads as follows:
- Google: Networking, FPGA/ASIC Hardware Engineer - Mountain View
- Mountain View, CA
Description:
This position is based in Mountain View, CA.
The area: Network Engineering, Production
The end result of our teams work is the delivery of Googles products
and services to users around the world. We build and operate Googles
production network, which connects the server farms in data centers to each other and to the Internet.
The role: Networking, FPGA/ASIC Hardware Engineer
Our Networking Hardware Design Engineers develop the next generation
networking products for all our services. This position targets the
need to develop complex FPGA and ASIC solutions that increase the level
of innovation in these networking solutions that help break industry
price/performance barriers. You should have a broad background in
LAN/WAN Ethernet networking HW design with an emphasis on FPGA/ASIC
design and verification.
Google deploys a wide range of technologies and hence is looking for
best of the breed Networking FPGA/ASIC Design/Verification Engineers
that have strong depth in multiple areas. You should have a proven
track record in FPGA/ASIC networking product development design and
verification, supported with a background in high speed digital design,
serial communication protocols, high speed memory systems, copper and
optical interconnect technologies and embedded processor subsystem
design.
Responsibilities:System Level HW Architecture.
Definition of Networking IP.
Design and Verification of FPGA/ASIC solutions.
Qualifications:
BS or MS in electrical or computer engineering or equivalent, with strong emphasis on networking product design preferred.
At least 5-10 years of network hardware architecture, design, and bring-up.
Thorough knowledge of component-level and integrated system testing.
10/100/1000/10000 Ethernet Experience.
PCI/PCI-E, Infiniband, Fiber-Channel.
IEEE Verilog, Physical Design and Timing Closure Experience.
FPGA/ASIC Verification experience with Vera/Specman/SystemVerilog/C++.
